1. Field of the Invention
The present invention relates to semiconductor circuit devices, and more particularly, to a semiconductor circuit device including a load circuit such as a sense amplifier.
2. Description of the Background Art
A typical example of a semiconductor circuit device is a semiconductor memory device. A semiconductor memory device includes various types of load circuits. A load circuit is supplied with power supply potential and ground potential via power supply interconnection and ground interconnection, respectively.
FIG. 17 is a block diagram schematically showing connection of a load circuit. Referring to FIG. 17, a power supply node N1 receives power supply potential V.sub.CC. A ground node N2 receives ground potential V.sub.SS. Power supply potential V.sub.CC is provided from power supply node N1 to a load circuit 5 via a power supply interconnection L1. Also, ground potential V.sub.SS is provided from ground node N2 to load circuit 5 via a ground interconnection L2. A parasitic interconnection resistance R1 exists in power supply interconnection L1. A parasitic interconnection resistance R2 exists in ground interconnection L2.
In the operation of load circuit 5 connected in the above-described manner, load current I1 flows from power supply node N1 to load circuit 5 via power supply interconnection L1, and load current I2 flows from load circuit 5 to ground node N2 via ground interconnection L2.
A sense amplifier for amplifying a signal is exemplary of such a load circuit. FIG. 18 is a circuit diagram of a semiconductor circuit forming a conventional sense amplifier circuit. Referring to FIG. 18, two sense amplifiers SA1 and SA2 are shown using a common power source as an example of a sense amplifier circuit.
Sense amplifier SA1 functions to amplify the potential difference between a pair of bit lines BL1 and /BL1. Sense amplifier SA2 functions to amplify the potential difference between a pair of bit lines BL2 and /BL2. Sense amplifiers SA1 and SA2 are provided between power supply node N1 receiving power supply potential V.sub.CC and ground node N2 receiving ground potential V.sub.SS.
Sense amplifier SA1 includes PMOS transistors Q1, Q2 and Q5, and NMOS transistors Q3, Q4, and Q6.
Transistors Q1 and Q2 have their sources connected to each other. Transistor Q1 has its drain and transistor Q2 has its gate connected to bit line BL1. Transistor Q1 has its gate and transistor Q2 has its drain connected to bit line /BL1.
Transistors Q3 and Q4 have their sources connected to each other. Transistor Q3 has its drain and transistor Q4 has its gate connected to bit line BL1. Transistor Q3 has its gate and transistor Q4 has its drain connected to bit line /BL1.
A node N3 between transistors Q1 and Q2 is connected to power supply node N1 via a transistor Q5 and power supply interconnection L1. Transistor Q5 receives a control signal .phi.2 at its gate for driving sense amplifiers SA1 and SA2. A node N4 between transistors Q3 and Q4 is connected to ground node N2 via a transistor Q6 and ground interconnection L2. Transistor Q6 receives a control signal .phi.1 at its gate for driving sense amplifiers SA1 and SA2.
In sense amplifier SA1 of the above-described structure, parasitic interconnection resistances R1 and R2 exit in power supply interconnection L1 and ground interconnection L2, respectively.
The structure of sense amplifier SA2 is similar to that of sense amplifier SA1. Sense amplifier SA2 has transistors Q7-Q12 connected in a manner similar to that of transistors Q1-Q6.
A memory cell MC1 is connected to bit line BL1. Memory cell MC1 includes a capacitor C1 for storing data and an NMOS transistor T1. Transistor T1 is connected between capacitor C1 and bit line BL1, and has its gate connected to a word line WL.
A memory cell MC2 is connected to bit line BL2. Memory cell MC2 includes a capacitor C2 for storing data and an NMOS transistor T2. Transistor T2 is connected between capacitor C2 and bit line BL2, and has its gate connected to word line WL.
The operation of the sense amplifier of FIG. 18 will be described hereinafter. First the operation of sense amplifier SA1 will be described.
By activation of word line WL, charge stored in memory cell MC1 is transferred to bit line BL1, whereby a slight potential difference is generated between bit lines BL1 and /BL1. Under this state, control signal .phi.1 attains a high level, and control signal .phi.2 attains a low level.
Here, the ON resistance of transistor Q1 becomes lower than that of transistor Q2 since the potential received at the gate of transistor Q1 is lower than that received at the gate of transistor Q2. Therefore, the potential of bit line BL1 is increased towards power supply potential V.sub.CC.
Also, the ON resistance of transistor Q4 becomes smaller than that of transistor Q3 since the potential at the gate of transistor Q4 is higher than that at the gate of transistor Q3. Therefore, the potential of bit line /BL1 is lowered towards ground potential V.sub.SS.
Therefore, the slight potential difference between bit lines BL1 and /BL1 is amplified with the potential difference between power supply potential V.sub.CC and ground potential V.sub.SS as a target value in sense amplifier SA1.
Sense amplifier SA2 carries out an operation similar to that of sense amplifier SA1. Therefore, the slight potential difference between bit lines BL2 and /BL2 is amplified with the potential difference between power supply potential V.sub.CC and ground potential V.sub.SS as a target value in sense amplifier SA2.
A semiconductor circuit may have a plurality of load circuits 5, one which is shown in FIG. 17, connected to one power supply interconnection L1 and one ground interconnection L2. FIG. 19 is a circuit diagram schematically showing a semiconductor circuit having a plurality of load circuits connected to one power supply interconnection and one ground interconnection.
Referring to FIG. 19, power supply interconnection L1 and ground interconnection L2 have a plurality of load circuits 51, 52, 53 and 54 connected thereto. In other words, the plurality of load circuits 51, 52, 53 and 54 share a power source.
In such a semiconductor circuit, there are respective connection nodes of load circuits 51-54 in power supply interconnection L1, and respective connection nodes of load circuits 51-54 in ground interconnection L2. In power supply interconnection L1, an interconnection resistance R11 exits between a connection node and power supply node N1. Also, respective interconnection resistances R12, R13 and R14 exit between respective connection nodes.
Similarly, in ground interconnection L2, an interconnection resistance R24 exits between a connection node of load circuit 54 and ground node N2. Also, respective interconnection resistances R21, R22, and R23 exist between respective connection nodes.
Load circuits 51-54 receive potentials V.sub.CC1, V.sub.CC2, V.sub.CC3, and V.sub.CC4 as power supply potential, and potentials V.sub.SS1, V.sub.SS2, V.sub.SS3, and V.sub.SS4 as ground potential, respectively.
Not all the load circuits of 51-54 are operated simultaneously, and there are cases when a load circuit is operated while another load circuit is not operated. Such an operating load circuit is called a selected circuit, and a load circuit not operating is called a de-selected circuit, hereinafter.
A typical example of one of load circuits 51-54 is a sense amplifier shown in FIG. 18. When each of load circuits 51-54 is a sense amplifier, load circuits 51-54 are divided into high readout sense amplifiers for reading out data of a high level from a memory cell, and low readout sense amplifiers for reading out data of a low level from a memory cell.
A control signal for driving the sense amplifier is applied simultaneously to a high readout sense amplifier and a low readout sense amplifier. When a control signal is applied simultaneously, a high readout sense amplifier initiates operation slightly before a low readout sense amplifier.
The reason thereof will be described hereinafter. For example, consider transistors Q3 and Q4 in FIG. 18. In the case of a high readout sense amplifier, transistor Q4 is turned on more deeply than transistor Q3 to lower the potential of bit line /BL1. In the case of a low readout sense amplifier, transistor Q3 is turned on more deeply than transistor Q4 to lower the potential of bit line BL1.
Here, transistor Q4 of the high readout sense amplifier is turned on before transistor Q3 of the low readout sense amplifier is turned on since the initial gate voltage of sense amplifier Q4 of the high readout sense amplifier is higher than the initial gate voltage of transistor Q3 of the low readout sense amplifier. Therefore, the high readout sense amplifier operates prior to the low readout sense amplifier.
Thus, in a semiconductor circuit including a high readout sense amplifier and a low readout sense amplifier as load circuits, there are cases when the low readout sense amplifier has not initiated operation when the high readout sense amplifier is already operating. It can be said that a high readout sense amplifier is one type of the aforementioned selected circuit, and a low readout sense amplifier is one type of the aforementioned de-selected circuit.
A conventional semiconductor circuit including a sense amplifier as a load circuit has problems set forth in the following.
Referring to the semiconductor circuit of FIG. 17, an operation of load circuit 5 causes load current I1 to flow from power supply node N1 to load circuit 5, and current I2 from load circuit 5 to ground node N2. A flow of load current I1 causes reduction in the potential due to interconnection resistance R1, whereby the potential in load circuit 5 from power supply node N1 becomes lower than power supply potential V.sub.CC. Also, a flow of load current I2 causes increase in the potential due to interconnection resistance R2, whereby the potential in load circuit 5 from ground node N2 becomes higher than ground potential V.sub.SS.
There is a possibility that load circuit 5 does not operate properly when the potential in load circuit 5 from power supply node N1 and ground node N2 varies. Particularly in the sense amplifier shown in FIG. 18, the following problem occurs.
Referring to FIG. 18, a flow of load current I1 causes the potential of node N3 to become lower than power supply potential V.sub.CC due to interconnection resistance R1. Also, a flow of load current I2 causes the potential of node N4 to become higher than ground potential V.sub.SS due to resistance R2. If the potential of node N3 becomes lower than power supply potential V.sub.CC and the potential of node N4 becomes higher than ground potential V.sub.SS in a sense amplifier, a sense operation will take a longer time period.
A possible consideration is to increase the width of the power supply interconnection and the ground interconnection in order to solve this problem. However, increase of the width of the power supply interconnection and the ground interconnection will yield the problem of increasing the occupying area of the interconnection in a semiconductor chip.
Referring to FIG. 19, operation of any of load circuits 51-54 which is a selected circuit causes load current to flow to power supply interconnection L1 and ground interconnection L2.
Such a flow of load current causes variation in potential V.sub.CC1 -V.sub.CC4 and V.sub.SS1 -V.sub.SS2 to be received by load circuits 51-54 according to interconnection resistances R11-R14 and R21-R24. Not only the potential entering a selected circuit of load circuits 51-54, but also the potential entering a de-selected circuit varies.
When load circuits 51-54 are sense amplifiers, variation in the potential received by a de-selected circuit due to operation of a selected circuit induces the following problem. When the potential entering a low readout sense amplifier which is a de-selected circuit is altered due to operation of a high readout sense amplifier which is a selected circuit to result in increase in the potential at the ground potential side, transistor Q3 of FIG. 18, for example, will not be turned on. Therefore, the low readout sense amplifier will not operate properly.
As described above, there was a problem that a sense amplifier functioning as a load circuit receiving potential via power supply interconnection and ground interconnection cannot operate properly due to variation in the potential by interconnection resistance.